Today's designs for system-on-chip (SoC) may have more than one hundred embedded memories on a single chip. These memories may be scattered around the device instead of being concentrated in one location. Typically, these memories are of different types and sizes. In addition, these memories may be further embedded inside embedded cores. This structure poses a challenge to testing all of the memories on the chips, as test access may be limited to only a few input/output (I/O) pins.
Built in self-test (BIST) is frequently used to test such embedded memories within SoCs, as it provides a simple and low cost method of testing that does not affect performance. Specific testing may be required to test all of the memories on a device, which is known as memory built-in self-test (MBIST). As SoCs are used ever more widely in devices, such as mobile phones, the challenge becomes offering increased performance while maintaining a portable device. As devices gain performance and functionality, the number of memories to support that functionality grows, as does the need to test those memories. This may lead to congestion at the MBIST controller as all data path routing must pass through the controller.
There is a need in the art for an architecture to reduce the amount of area required to provide MBIST functionality and also to reduce MBIST controller to data path routing congestion without affecting the quality of resilience (QoR) of the device.